1. Field of the Invention
The present invention relates to an MIS (Metal Insulator Semiconductor) structure semiconductor apparatus made on Silicon On Insulator (SOI). More particularly, the present invention relates to a semiconductor apparatus such as an MOS (Metal Oxide Semiconductor) achieving both high-speed operation and low leakage current, and complimentary MIS logic circuit made using this semiconductor apparatus.
2. Description of Related Art
In the related art, it is well-known that, in order to make MOS transistors themselves high-speed, in addition to miniaturizing the semiconductor elements and making gate lengths of MOS transistors shorter, lowering threshold voltage is extremely effective. However, there is a tendency for sub-threshold leakage current that is unnecessary current flowing between a source and a drain to increase as the threshold voltage is lowered. Various technology has therefore been reported to implement countermeasures so that sub-threshold leakage current does not increase.
For example, static RAM that suppresses sub-threshold leakage current by applying a back-bias voltage to a silicon substrate only at the time of standby so as to increase the threshold voltage of a MOS transistor is known, as in patent document 1 (Japanese Patent Laid-open Publication No. Hei. 7-211079). According to this technology, a ground voltage VSS=0V is supplied as a back-bias voltage for a driver transistor at the time of an access. When a threshold voltage of a driver transistor is then, for example, 0.4V, at the time of a standby state, a negative voltage VAA=−2V is supplied as a back-bias voltage for the driver transistor, and a threshold voltage for the driver transistor is made, for example, 0.9V. As a result, it is possible to raise the threshold voltage from 0.4V to 0.9V and increases in the sub-threshold leakage current can be suppressed.
Further, in Japanese patent document 2 (Japanese Patent Laid-open Publication No.Hei.11-307652), circuits inviting a substrate bias effect by utilizing capacitor coupling using a buffer output signal of the same phase as a gate signal are known for pass transistor logic employing NMOS transistors. According to this technology, in the event that a pair of output signals from logic circuits configured with pass transistor logic employing NMOS transistors are buffered using CMOS inverters, an output terminal of one of the CMOS inverters and a channel region of a transistor constituting the other CMOS inverter are respectively capacitor-coupled via a silicon substrate. An output signal of a CMOS inverter for which a rising level transition is fast from the time where an input signal changes is then applied to a silicon substrate of a transistor on the side of the other CMOS inverter. The drive power of the transistor is then increased by this substrate bias effect and a rising level transition for an output signal of the other CMOS inverter is made faster.
Further, in another embodiment of Japanese patent document 2, in the event that an output signal from a logic circuit configured with pass transistor logic employing NMOS transistors is buffered using a CMOS inverter, an inverted signal is made from the output signal of this inverter via a separate CMOS inverter. This signal and the channel region of the transistor constituting the first CMOS inverter are capacitor-coupled via a silicon substrate. As a result, it is possible to cause a substrate bias effect.
Further, in patent document 3 (U.S. Pat. No. 6,213,869), technology is disclosed where substrate potential shifts to a forward bias side when a MOS transistor goes on as a result of utilizing gate capacitance between a gate of a MOS transistor formed on a floating substrate and the substrate so as to stabilize the voltage at which a BJT (Bipolar Junction Transistor) formed in parallel with the MOS transistor goes on. This means that the threshold voltage of the MOS transistor becomes small and the drive power becomes high. Conversely, when the MOS transistor goes OFF, the substrate potential shifts to the back-bias side. Lower power consumption increased can then be achieved due to the threshold voltage of the MOS transistor being large.
However, the method of suppressing the sub-threshold leakage current disclosed in patent document 1 requires a circuit for applying the substrate bias and this causes the semiconductor apparatus to become large and costs to increase. Further, with the technology disclosed in patent document 2, a pair of signals of normal and reverse phases such as with pass transistor logic are necessary, which means that signal circuits become complex. Moreover, with the technology of another embodiment of patent document 2, a CMOS inverter is necessary every one output. This means that if the number of outputs is large, the circuit scale also becomes large.
Further, in Japanese patent document 3, as a result of transistor sizes becoming more and more miniaturized, gate surface areas are reducing and gate capacitances of MOS transistors on floating substrates are getting smaller. Moreover, voltages applied to gates are also becoming lower in accompaniment with power supply voltages becoming lower. As a result, when a gate voltage is applied in order to put a MOS transistor ON, cases where a change in substrate potential resulting from the gate capacitance no longer exceeding a clamp voltage VC of a diode constructed from the base and emitter of the BJT occur, and the substrate potential therefore becomes unstable.